1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having memory cells, and in particular, a semiconductor integrated circuit having a delayed write function.
2. Description of the Related Art
Semiconductor integrated circuits are in the process of becoming faster and faster in line with the development of semiconductor manufacturing technology. Particularly, the operating frequency of a microcomputer, etc., has been improved year by year, wherein a difference between the operating frequency thereof and that of a semiconductor memory such as DRAMs, etc., has become remarkable. In order to reduce the difference, a high-rate memory such as SDRAMs (synchronous DRAMS), etc., has been developed.
Further, recently, in order to improve the using rate of a data bus, an SDRAM has been developed, which has a so-called xe2x80x9cdelayed writexe2x80x9d (or xe2x80x9clate writexe2x80x9d) function by which write data provided with respect to a write command are written in a memory cell when providing a next write command.
FIG. 1 shows an example that performs a write operation during read operations in an SDRAM having this type of delayed write function. In this example, the read latency that is the number of clock cycles from acceptance of a read command to output of the read data is set to xe2x80x9c2xe2x80x9d. Also, the write latency that is the number of clock cycles from acceptance of a write command to acceptance of write data is set to xe2x80x9c2xe2x80x9d.
First, read commands RD0 and RD1 are provided sequentially in synchronization with a clock signal CLK, and a memory core unit operates (FIG. 1(a)). Although not particularly illustrated, a read address is supplied along with the read command. The memory core outputs read data with a delay of approximately 1 clock from the acceptance of the read command. After that, an input/output circuit operates (FIG. 1(b)).
Read data Q00, Q01, Q10, and Q11 are outputted sequentially with a delay of two clocks from the acceptance of the respective read commands RD0 and RD1 as a data signal DQ. The read data Q00 and Q01 or Q10 and Q11 are generated by converting parallel read data, which are transmitted through the interior of the chip to serial read data.
A write command WR0 is provided after two clocks from the acceptance of the read command RD1. In this example, since the write latency is xe2x80x9c2xe2x80x9d, write data DA0 and DA1 are provided with a delay of two clocks from the write command WR0. That is, the write data DA0 and DA1 are provided in synchronization with the clock signal after the read data Q11 is outputted (FIG. 1(c)). At this time, the write data DA0 and DA1 are not written in the memory cells, but are held in a register (FIG. 1(d)).
After that, the read commands RD2, RD3 and RD4 are provided sequentially in synchronization with the next clock signal of the write command WR0, and a read operation is performed at the same timing as described above (FIG. 1(e)). Since the memory core unit does not perform any write operation, it can instantaneously perform the read operation. Therefore, in a SDRAM having a delayed write function, the period in which no data signal DQ is transmitted is minimized, and the using rate of the data bus can be improved.
A next write command WR1 is provided after two clocks from the acceptance of a read command RD4 (FIG. 1(f)). The input/output circuit and the memory core unit operate in synchronization with the acceptance of the write command WR1, and the previous write data DA0 and DA1 that are held in the register are written in the memory cells (FIG. 1(g)).
Next, write data DA2 and DA3 are provided with a delay of two clocks from the write command WR1. The contents of the register are re-written to the write data DA2 and DA3 (FIG. 1(h)).
Thus, in the SDRAM having a delayed write function, it is possible to perform a write operation in the memory cells separately from the intake timing of the write data. At this time, it is possible to prevent the operation of the memory core unit corresponding to the write command from overlapping the operation of the memory core unit corresponding to the read command that is provided immediately after the write command. As a result, the using rate of the data bus can be improved compared with conventional SDRAMs, wherein a large amount of data can be transferred.
However, the SDRAM having a delayed write function is a technology that has been recently proposed, wherein there are some items to be taken into consideration for the commercial use thereof.
For example, where the read address corresponding to the above-described read command RD2 is the same as the write address corresponding to the write command WR0, the SDRAM must output the write data, which are held in the register, as the read data. However, in the SDRAM having a delayed write function, detailed circuits to achieve the function are not taken into consideration.
It is therefore an object of the invention to provide a semiconductor integrated circuit having a delayed write function that performs the read operation without fail.
According to one of the aspects of a semiconductor integrated circuit of the present invention, the semiconductor integrated circuit includes a memory cell, an address holding part, a data holding part, an address comparison part, and a data selecting part. The address holding part holds a write address which is supplied corresponding to a write command, as a held write address. The data holding part holds write data provided corresponding to the write command as held write data, and writes the held write data held corresponding to the previous write command, to a memory cell corresponding to the held write address when receiving the next write command. The address comparison part has a plurality of address comparators that compare a read address, which is supplied corresponding to a read command, with a held write address, by a plurality of bits. When the result of comparison of the address comparison part is coincident, or in agreement in a read operation, the held write data are outputted as read data. When the results of comparison of the address comparison part are not coincident, data from the memory cell are outputted as read data.
Since the read address and the held write address are compared by a plurality of address comparators, the scale of circuits in the address comparison part can be reduced. In addition, the address comparison can be performed at a high rate, so that the read operation can be performed at a high rate.
According to another aspect of a semiconductor integrated circuit of the invention, the address comparison part includes address comparators each corresponding to a row address and a column address. The row address and the column address are transmitted at almost the same timing, taking just about the same path, respectively. Therefore, by dividing the read address and held write address to a row address and a column address, and comparing them in different address comparators, the addresses can be efficiently compared. That is, address comparison is performed at a high rate.
According to still another aspect of a semiconductor integrated circuit of the invention, a predetermined address comparator operates in response to when comparison made by another address comparator results in a coincidence. For example, a part of the read address and a part of the held write address which are transmitted through the chip earlier, are compared by an predetermined address comparator. Another part of the read address and another part of the held write address which are transmitted through the chip later, are compared by another address comparator when the results of comparison by the predetermined address comparator are coincident. When the results of comparison by the predetermined address comparator are not coincident, the other address comparator does not operate. As a result, the power consumption can be reduced.
According to yet another aspect of a semiconductor integrated circuit of the invention, the semiconductor integrated circuit includes address comparators each corresponding to a row address and a column address. Parts of the row address and the column address are supplied sequentially through the same address terminal. And, the address comparator corresponding to the column address operates according to the result of comparison the address comparator corresponding to the row address. Therefore, the comparison of the row address is enabled before the column address is supplied, so that the read address and the held write address are compared at a high rate.